The present invention generally relates to reuse of a logical operations functional block in an execution unit of a processor.
Processors, e.g., microprocessors, are commonly known in the information technology industry. Today, practically all processors are compliant with the von-Neumann architecture and have similar functional blocks. Most processors include a load-store unit, a fixed-point unit, a floating-point unit, and a vector unit. Additionally, and as part of an execution unit, a set of registers may be present in a processor. A processor may include several general purpose registers. A floating-point unit may include a vector register file that may be a continuous bank of registers that may be accessed. A register is typically several bits wide, depending on the word size of the processor. Today, typical word sizes are 32, 64, and also 128 bits. Due to several factors, the content of some of the registers may change unintentionally and, thus, contain a “wrong” bit sequence. A wrong bit in a word may be detected by either additional parity bit(s) stored together with a data word or other error correction code (ECC) information. Moreover, the location of the bit error within a data word may be detected by an ECC and may then be corrected. In general, known techniques utilize special hardware for bit error correction or rely on calling complex microcode subroutines that also employ special hardware components for bit error correction. The wrong bits, e.g., soft errors, in a register may be produced by noise on the data-lines and/or word-lines (or other lines within the processor) or may be produced by random alpha particles striking a circuit within a processor.
In general, ECC correction units are known. For example, U.S. Patent Application Publication No. 2011/0154157 discloses a method for generating hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic Hammer code, includes a first residual code (based on a data block), a first parity code (based on the data block), and a Hammering matrix. The generated code, along with the data block, can then be communicated through at least a portion of a data-path of a processor. As another example, U.S. Pat. No. 6,934,903 discloses an apparatus that may include an ECC check circuit configured to detect an ECC error in response to an access to first data in a memory and a microcode unit. The microcode unit receives an indication that the ECC check circuit has detected an ECC error. In response to the indication, the microcode unit is configured to dispatch a microcode routine stored in the microcode unit.